1. Field of the Invention
The present invention pertains to the field of control units for implementing direct memory access (DMA) techniques. In particular, the present invention pertains to a DMA unit that can be programmed to optimize the DMA interface, based on the characteristics and configuration of the memory and input/output (I/O) devices of a computer system.
2. Description of the Related Art
In a microprocessor-based computer system, a DMA controller can facilitate the transfer of data between an I/O device and a memory unit, without the direct control of the central processing unit (CPU). Data can either be transferred from memory to an I/O device (a memory source transfer) or from an I/O device to memory (a memory destination transfer). Data can also be transferred between two memory units, but, in that situation, one of the memory units is considered an I/O device for purposes of the present description. DMA transfers typically involve the transfer of one or more blocks of data, as data transfers of only a few bytes of data are often performed more efficiently under the direct control of the CPU.
A DMA transfer is typically accomplished in the following manner. First, the CPU initializes both the DMA controller and the I/O device by indicating, for example, a source address, a destination address, and the amount of data to be transferred. Next, the DMA controller generates address and control signals to control the system I/O bus to perform successive data transfers until all of the requested data have been transferred from the source to the destination. During the successive data transfers the source responds to the address and control signals generated by the DMA controller to transmit the requested data, and the destination responds to the address and control signals generated by the DMA controller to receive the data. After the DMA transfer is complete, the DMA controller may notify the CPU of this condition by activating an interrupt, or, alternatively, the CPU may poll the DMA controller to determine when the DMA transfer is complete.
If two addresses must be generated on the same bus to complete a data transfer, the DMA controller typically performs two consecutive bus cycles. In the first cycle, the DMA controller generates the appropriate source address, and data are transferred from the source to the DMA controller. In the second cycle, the DMA controller generates the appropriate destination address, and data are transferred from the DMA controller to the destination. The DMA controller buffers the data between the two bus cycles.
DMA transfers can significantly improve system performance because the CPU is able to perform other functions while the data transfers are occurring. However, existing DMA controllers are not efficient in their use of either memory buses or I/O buses. The rate of DMA transfers is generally limited by relatively slow I/O devices. While the DMA controller and the memory are waiting for the I/O device to complete a data transfer, the memory bus is often tied up, preventing the CPU from performing other memory accesses, and the I/O bus is often tied up, preventing various other I/O transfers.